1. Technical Field
Various embodiments generally relate to a sense amplifier and a semiconductor device including the same, and more particularly, to a technology relating to a sense amplifier for reading the data of a semiconductor device.
2. Related Art
A semiconductor device includes memory cells and a plurality of data input/output lines for performing data input/output operations on a memory. The data is moved through data input/output lines. The data input/output lines include bit lines, local input/output lines, and global input/output lines. The paths of the data input/output lines used to input and output data are substantially long.
The loads of the data input/output lines electrically interconnected are different from one another. As the chip size of a semiconductor memory device increases, the lengths of data lines playing the role of transmitting data also increase. Accordingly, increases in data transmission delays inevitably occur in the data lines by capacitive loading of the data lines. In an effort to promote smooth data transmission, a semiconductor memory device implements a sense amplifier for amplifying data.
In a semiconductor memory device, data outputted from a memory cell has a substantially fine level of potential. Such a fine signal primarily passes through a bit line sense amplifier, secondarily passes through a local line sense amplifier, is thirdly sensed and amplified by a data input/output line sense amplifier (IOSA), and is discriminated as data of a logic low or a logic high.
Semiconductor memory devices are being developed towards reducing an operation power supply voltage, in consideration of power consumption and reliability. As the operation power supply voltage of the semiconductor memory devices decrease, the potential of a data signal outputted from a memory cell becomes further feeble, and the difference between the potentials of a bit line pair to be applied to the input terminals of a sense amplifier becomes gradually fine.
As a semiconductor memory device trends toward high speed operation, a time during which data lines are activated is shortened. Thus, the difference in the potentials of the bit line pair decreases, whereby a data signal sensing operation becomes further difficult.